The present invention relates to memory systems in computer systems. More specifically, the present invention relates to an apparatus for implementing a buffered daisy chain ring connection between a memory controller and memory modules.
Memory modules such as the Dual In-Line Memory Module (DIMM) have become a popular memory packaging design. DIMMs are small printed circuit boards mounted with a plurality of memory devices. DIMMs have leads accessible via both sides of a printed circuit board""s electrical connector unlike its predecessor, the Single In-Line Memory Module (SIMM), which has leads on only one side of the printed circuit board""s electrical connector. DIMMs are inserted into small socket connectors that are soldered onto a larger printed circuit board, or motherboard. A plural number of memory modules are usually typically directly connected to a memory controller via multi-drop connections to a memory bus that is coupled to the memory side of the memory controller. The memory controller transmits and receives memory data via the memory bus. Each of the memory modules includes a plurality of memory devices mounted on the memory module. The memory devices typically are Dynamic Random Access Memory (DRAM).
FIG. 3 illustrates an end on view of a conventional multi-drop routing between a memory controller 111 and two exemplary memory modules 210-211. The memory bus 310 connects to each of the memory devices 210a and 210b through a stub. Stub 310a connects the bus 310 to memory devices 211a. Stub 310b connects the bus 310 to memory devices 211b. The stub introduces a capacitive load discontinuities to the signal being carried to the memory devices 211a and 211b by the bus 310. Furthermore, the stubs directly connect to the memory devices without any intermediary signal conditioning including a voltage translation.
A drawback to memory modules directly connected to a memory bus via multi-drop connections is that there is no voltage level isolation between the memory devices and the memory controller. This lack of voltage isolation does not permit a variance between the voltage level of memory device inputs and memory controller outputs on the one hand, and memory device outputs and memory controller inputs on the other hand. Thus, in a system in which the signal level of a memory controller is below the memory device permissible range, the memory device will not recognize inputs, and memory device outputs will exceed the safe operating level of the memory controller or a coupled CPU.
Another drawback to memory modules directly connecting to a memory bus via multi-drop connections is that there is no capacitive load isolation between the multi-drop bus and the memory devices causing memory device operation that is slower than it would be without the multi-drop line capacitive load.
Another drawback to memory modules coupled to a memory bus via multi-drop connections is that the peak data rate per line on the memory bus is smaller than it would otherwise be because the discontinuities on a multi-point bus have an impedance that increases with frequency. This lower peak data rate per line places a higher floor on the number of pins connecting to a memory module for a given signal that would otherwise be for a point-to-point connection.
According to an embodiment, a memory module includes at least one memory device and a junction circuit. The junction circuit has a first port to couple to a bus from alternatively a memory controller and a daisy-chained other memory module. The junction circuits has a second port coupled to the memory devices, and a third port to couple to a bus from alternatively a memory controller or a daisy-chained other memory module. The junction circuit sends data received from the first port to the second port and the third port, sends data received from the second port to the first port and the third port, and send data received from the third port to the second port and the first port. The junction circuit also includes an isolation circuit to provide a point-to-point connection to the first port and the third port, and a data synchronization circuit in electrical communication with the first port, the second port, and the third port to synchronize the data input to the first port with the data input to the third port.